In the manufacture of integrated circuits it is desirable to provide overvoltage/backdrive protection for input/output structures. It is desirable to provide an overvoltage/backdrive protection circuit that is capable of preventing reverse charge leakage and gate oxide breakdown when the voltage on an input/output structure exceeds an internal power supply voltage or when the input/output structure is powered down.
The term “backdrive” refers to a condition that may occur when a device that is powered down is connected to a bus to which other devices are also connected. When one of the other devices is powered up and begins driving the bus, the device that is powered down may receive a “backdrive” voltage signal from the bus.
Different types of Metal Oxide Semiconductor (MOS) transistors can be fabricated and used in electronic circuits. For example, thick gate transistors and thin gate transistors can be used in electronic circuits, where the thick gate transistors and the thin gate transistors have gate oxide layers of different thicknesses. The term “thin gate transistor” refers to a transistor that has a gate thickness of ninety Ångstroms (90 Å) or less. The term “thick gate transistor” refers to a transistor that has a gate thickness of one hundred ten Ångstroms (110 Å) or more. In one advantageous embodiment, the thin gate transistors have a gate thickness of about seventy Ångstroms (70 Å) and the thick gate transistors have a gate thickness of about one hundred thirty Ångstroms (130 Å).
For another example, standard, native, and depletion n-channel MOS (NMOS) transistors can be used in electronic circuits. A standard NMOS transistor is typically formed within a p-well, a native NMOS transistor is typically formed directly on a semiconductor substrate, and a depletion NMOS transistor is typically formed within a p-well that has a special depletion implant in the gate region of the transistor.
The different types of transistors typically have different operating characteristics. For example, a gate to source voltage (VGS) that is equal to (or nearly equal to) zero volts may be needed to turn off a thick-gate standard NMOS transistor. A gate to source voltage that is equal to a negative three hundred fifty millivolts (−350 mV) may be needed to turn off a thick gate native NMOS transistor. A gate to source voltage that is equal to a negative five hundred millivolts (−500 mV) to a negative six hundred millivolts (−600 mV) may be needed to turn off a thick gate depletion NMOS transistor. A gate to source voltage that is equal to a negative two hundred millivolts (−200 mV) may be needed to turn off a thin gate standard NMOS transistor.
In certain electronic circuits, this means that native and depletion NMOS transistors cannot be turned completely off, such as when a source voltage rail (VDD) is one and eight tenths volts (1.8 V) and a ground voltage rail (VSS) is zero volts (0.0 V). The inability to completely turn off native and depletion NMOS transistors often prevents the native and depletion NMOS transistors from being used in standard logic gates and other circuits.
The specifications for an input/output structure of an exemplary bus structure require an output voltage range of one volt (1.0 V) to one and one half volt (1.5 V). This requirement gives rise to problems in providing robust electrostatic discharge (ESD) performance and acceptable alternating current (ac) performance. In order to achieve good ESD performance it is desirable to allow only thick gate transistors to touch the output pad of the input/output structure.
A major problem with this approach is that at room temperature (about twenty three degrees Celsius (23° C.)) the threshold voltage (Vth) for a thick gate PMOS transistor is typically nine tenths of a volt (0.9 V). As the temperature drops to about minus forty degrees Celsius (−40° C.), the threshold voltage (Vth) will climb to about one and one tenth volt (1.1 V). This means that the amount of overdrive voltage of a PMOS transistor (i.e., the gate to source voltage (VGS) minus the threshold voltage (Vth)) becomes very small.
For example, at minus forty degrees Celsius (−40° C.), the overdrive voltage of a PMOS transistor can be as little as one tenth of a volt (0.1 V). This is because the ground to source voltage VGS is one and two tenths volt (1.2 V) and the threshold voltage (Vth) is one and one tenth volt (1.1 V). The difference (1.2 V−1.1 V) is one tenth of a volt (0.1 V). Therefore, the ability of a PMOS transistor to provide a sufficient drive is severely limited.
One method for avoiding this result would be to have a second voltage on board the input/output structure. The second voltage could have a value of two and one half volts (2.5 V) or three and three tenths volt (3.3 V). The second voltage could be used in the output PMOS transistor. This approach requires special level shifters to transform the core voltage range of one and one half volt (1.5 V) (or one and two tenths volt (1.2 V)) down to zero volts (0.0 V) into a larger range of two and five tenths volts (2.5 V) (or three and three tenths volt (3.3 V)) down to zero volts (0.0 V).
There are several drawbacks with this method. First, the special lever shifters will limit the alternating current (ac) performance of the input/output structure. Second, a second voltage will have to be provided. Third, the input side of the input/output structure still must operate with a gate to source voltage (VGS) of one and two tenths volt (1.2 V) or one and five tenths volt (1.5 V). These drawbacks could be overcome with specially designed linear input/output structures that draw ac current. However, this would provide an undesirable increase in the amount of current consumption in the input/output structure.
FIG. 1 illustrates a schematic circuit diagram of a first prior art input/output structure 100. As shown in FIG. 1, input/output structure 100 comprises four thick gate transistor devices (M1, M2, M3, M4). The drain of thick gate NMOS transistor M1 and the drain of thick gate PMOS transistor M2 are connected to the PAD node (also designated as node “a23”). The source and body of thick gate PMOS transistor M2 are connected to the external supply voltage VDDIO and the source and body of thick gate NMOS transistor M1 are connected to the ground voltage VSS. The gate of thick gate NMOS transistor M1 and the gate of thick gate PMOS transistor M2 are connected to the output of an inverter 110. The inverter 110 provides an inverted version of the input signal to the gate of the thick gate NMOS transistor M1 and to the gate of the thick gate PMOS transistor M2. The input of inverter circuit 110 is connected to an input node “a5” (designated with the word INPUT in FIG. 1).
As also shown in FIG. 1, the gate of thick gate PMOS transistor M3 and the gate of thick gate NMOS transistor M4 are connected to the PAD node. The source and the body of the thick gate PMOS transistor M3 are connected to the external supply voltage VDDIO. The source and the body of the thick gate NMOS transistor M4 are connected to the ground voltage VSS. The drain of thick gate PMOS transistor M3 and the drain of thick gate NMOS transistor M4 are both connected to the PAD Y INPUT.
One major drawback of the prior art input/output structure 100 shown in FIG. 1 is that the switching transistors (M1 and M2) are both thick gate devices. This means that the P channel device (PMOS transistor M2) has a room temperature threshold voltage (Vth) of approximately eight tenths of a volt (0.8 V). At low temperatures the threshold voltage will be even larger (perhaps as much as one volt (1.0 V)).
This means that at a low temperature and a low voltage the overdrive of the P channel device (PMOS transistor M2) would be small and the alternating current (ac) performance would be poor. At low values of the external supply voltage VDDIO, the performance of the thick gate input/output structure 100 becomes compromised and performs very poorly.
In order to compensate for the poor performance at low temperature and low voltage, the sizes of the switching transistors (M1 and M2) may have to be increased to very large sizes—perhaps to twenty (20) or thirty (30) times the size of thin gate MOS devices driving the same conditions.
FIG. 2 illustrates a schematic circuit diagram of a second prior art input/output structure 200. As shown in FIG. 2, there are only two transistors (NMOS transistor M0 and PMOS transistor M6) that touch the PAD node. The PAD node is coupled to an electrostatic discharge (ESD) structure (not shown in FIG. 2). The NMOS transistor M0 and the PMOS transistor M6 are both thick gate transistors. The remaining transistors (M1, M2, M3, M4, M5) are thin gate transistors. The thick gate transistors (M0, M6) form the transfer gate of input/output structure 200.
The drain of NMOS transistor M0 and the drain of PMOS transistor M6 are both connected to the PAD node. The body of NMOS transistor M0 is connected to the ground voltage VSS. The body of PMOS transistor M6 is connected to the external power supply voltage VDDIO. The source of NMOS transistor M0 and the source of PMOS transistor M6 are both connected to the drain of PMOS transistor M2 and to the drain of NMOS transistor M1. The source and body of PMOS transistor M2 are connected to the external power supply VDDIO. The source and body of NMOS transistor M1 are connected to the ground voltage VSS. The gate of NMOS transistor M1 and the gate of PMOS transistor M2 are connected to control signals that appropriately turn transistors M1 and M2 on and off.
The gate of PMOS transistor M6 is connected to an inverted version (ENZ) of the enable signal (EN). The inverted version (ENZ) of the enable signal (EN) is the signal that is used to enable the output driver. The gate of NMOS transistor M0 is connected to the drain of NMOS transistor M4 and to the drain of PMOS transistor M5. As shown in FIG. 2, the gate of NMOS transistor M4 and the gate of PMOS transistor M5 are coupled to the inverted version (ENZ) of the enable signal (EN). The source and body of NMOS transistor M4 are connected to the ground voltage VSS and the source and body of the PMOS transistor M5 are connected to the external supply voltage VDDIO.
Transistor M3 is a PMOS transistor that has its gate coupled to the enable signal (EN) and its source and body connected to the external supply voltage VDDIO. The thin gate output driver is enabled when the enable signal (EN) is high. The drain of PMOS transistor M3 is connected to the source of NMOS transistor M0 and to the source of PMOS transistor M6 and to the drain of PMOS transistor M2 and to the drain of NMOS transistor M1.
The second prior art structure 200 shown in FIG. 2 provides a thin gate transistor output driver in which only thick gate transistor devices (M0, M6) are in contact with the PAD node. The threshold voltage (Vth) for a thin gate PMOS transistor is approximately one half volt (0.5 V). The threshold voltage (Vth) for a thin gate NMOS transistor is approximately four tenths of a volt (0.4 V). This means that the thin gate transistors can provide a reasonable performance level.
One drawback of the prior art input/output structure 200 is that there is a problem with charge leakage from the PAD node when the temperature reaches one hundred twenty five degrees Celsius (125° C.). Another drawback of the prior art input/output structure 200 is that if the output is active (and the transfer gate (M0, M6) is enabled) and an electrostatic discharge (ESD) event occurs, the ESD event will likely go straight to the thin gate transistors and cause them to fail. In addition, there are two thick gate transistor devices (transfer gate transistors (M0,M6)) in the ac path. Even though the transfer gate transistors (M0, M6) are enabled and may not switch in an ac mode, the overdrive of these two devices would be very small. This would require the size of the transistor M1 and the size of transistor M2 and the size of the transfer gate transistors (M0, M6) to be very large (assuming that they can be made large enough to perform their required functions).
Therefore, there is a need in the art for an improved system and method of providing overvoltage/backdrive protection for an input/output structure. In particular, there is a need in the art for an improved system and method for providing a low voltage, thin gate input/output structure with thick gate overvoltage/backdrive protection.
The present invention provides an improved system and method for providing overvoltage/backdrive protection for an input/output structure. In one advantageous embodiment of the present invention, a transfer gate of the input/output structure comprises a thick gate native or depletion n-channel metal oxide semiconductor (NMOS) transistor that is connected to an output pad node of the input/output structure. The thick gate native or depletion NMOS transistor prevents current from the output pad node from entering the input/output structure when the voltage level at the output pad node is high.
Before undertaking the Detailed Description of the Invention below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like.
Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior uses, as well as to future uses, of such defined words and phrases.